1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly to the arrangement of peripheral circuits in a semiconductor memory device. More particularly, the present invention relates to the arrangement of peripheral circuits for achieving high speed accessing to a Dynamic Random Access Memory.
2. Description of the Background Art
FIG. 9 is a diagram schematically showing the configuration of a memory mat in a conventional semiconductor memory device. In FIG. 9, memory mat MM is divided into a plurality of memory blocks MB#0 to MB#m each having a plurality of memory cells arranged in rows and columns. Between these memory blocks MB#0 to MB#m arranged are sense amplifier bands SB#1 to SB#m each of which detects and amplifies data on columns in a corresponding memory block when activated, and further provided outside memory blocks MB#0 and MB#m are sense amplifier bands SB#0 and SB#n, respectively. More specifically, sense amplifier band SB#1 is shared between memory blocks MB#0 and MB#1 on its both sides, and sense amplifier band SB#m is shared between memory blocks MB#m and MB#m-1 (not shown). A configuration having these sense amplifier bands SB (generally representing sense amplifier bands SB#1 to SB#m) between facing memory blocks is known as "shared sense amplifier configuration", in which a selected memory block (a block including a selected memory cell) is connected to a corresponding sense amplifier band, a non-selected memory block, the other of the paired memory blocks is electrically separated from the corresponding sense amplifier band. If the memory blocks on both sides of the sense amplifier band are both non-selected memory blocks (which include no selected memory cell), these memory blocks are connected to the sense amplifier band to keep their precharged states.
A row related circuit RRC for performing an operation related to selecting a row of memory cells is provided along a longer side of the memory mat MM, and a column decoder CD is provided adjacent to sense amplifier band SB#n. Row related circuit RRC include row decode circuits provided corresponding to memory blocks MB#0 to MB#m. The row decode circuit drives into a selected state a word line WL corresponding to a memory cell row addressed in response to an address signal applied through a path not shown. In FIG. 9, a single word line WL is shown in memory block MB#1 by way of illustration Word line WL is provided only in one memory block and along the direction of a shorter side of memory mat MM.
Meanwhile, column decoder CD decodes an address signal (not shown), and produces a column select signal to select an addressed column. The column select signal from column decoder CD is transferred onto a column select signal transmission line CSL. Column select signal transmission line CSL is provided extending along the longer side direction of memory mat MM and over all the memory blocks MB#0 to MB#m so as to be shared among all the memory blocks MB#0 to MB#m.
In the configuration of memory mat MM in FIG. 9, a prescribed number of memory blocks, one or two memory blocks for example, out of memory blocks MB#0 to MB#m are driven into a selected state, and data are written/read to/from the selected memory blocks. Thus, all the memory blocks MB#0 to MB#m are not activated, but only a prescribed number of memory blocks are activated to reduce current consumption.
FIG. 10 is a diagram schematically showing one memory block and sense amplifier bands on its both sides in the memory mat shown in FIG. 9. In FIG. 10, the configuration of memory block MB#i is schematically shown.
In FIG. 10, memory block MB#i includes a plurality of memory cells MC arranged in rows and columns, a plurality of word lines WL0 to WLn each having memory cells MC in a corresponding row connected thereto, and a plurality of bit line pairs BLP provided corresponding to respective columns of memory cells MC and each having memory cells MC in a corresponding column connected thereto. In FIG. 10, three bit line pairs BLP0, BLP1 and BLP2 are shown by way of illustration. Bit line pairs BLP0 to BLP2 each include bit lines BL and /BL which transfer data signals complimentary with each other. Memory cells MC are provided corresponding to crossings of word lines WL (generally representing WL0 to WLn) and bit lines BL and /BL.
Sense amplifier band SB#i provided between memory blocks MB#i-1 and MB#i includes a sense amplifier SAaj+1 provided corresponding to an odd-numbered bit line pair BLPj+1 of these memory blocks MB#i-1 and MB#i. In FIG. 10, sense amplifier SAa1 provided corresponding to bit line pair BLP1 is shown by way of illustration. Adjacent to sense amplifier SAa1, a bit line equalize circuit EQ for equalizing a corresponding pair of bit lines to a prescribed intermediate potential VBL when activated is provided. The equalize circuit is also represented by equalize circuit EQa1 adjacent to sense amplifier SAa1 by way of illustration in FIG. 10.
A sense amplifier (SAa1) in sense amplifier band SB#i is connected to an odd-numbered bit line pair (BLP1) in memory block MB#i-1 through a bit line isolation gate IGca which conducts in response to a bit line isolation control signal BLIa0, and is electrically connected to an odd-numbered bit line pair (BLP1) in memory block MB#i through a bit line isolation gate IGaa (IGaa1) which conducts in response to a bit line isolation control signal BLIa1.
Sense amplifier band SB#i+1 includes sense amplifiers SAb (SAb0, SAb2 . . . ) provided corresponding to even-numbered bit line pairs (BLP0, BLP2, . . . ) in memory block MB#i and MB#i+1 which is not shown.
Sense amplifier band SBi+1 further includes bit line equalize circuits EQb (EQb0, EQb1, . . . ) provided adjacent to sense amplifiers SAb (SAb0, SAb2, . . . ) to precharge and equalize a corresponding bit line pair BLP (BLP0, BLP2, . . . ) into an intermediate potential level.
Sense amplifiers SAb (SAb0, SAb2, . . . ) in sense amplifier band SB#1+1 are electrically connected to even-numbered bit line pairs BLP (BLP0, BLP2, . . . ) in a corresponding memory block MB#i through bit line isolation gates IGab (IGab0, IGab2, . . . ) which conduct in response to a bit line isolation control signal BLIb.
Sense amplifiers SAb (SAb0, SAb1, . . . ) in sense amplifier band SB#i+1 are also electrically connected to even-numbered bit line pairs in memory block MB#i+1 which is not shown through corresponding bit line isolation gates.
Row related circuit RRC corresponding to memory block MB#i includes a row decode circuit RD which decodes an internal address signal (which includes an address to designate a memory block) and produces a signal to select a word line corresponding to a row addressed in memory block MB#i, and word line drive circuits WD0 to WDn provided corresponding to word lines WL0 to WLn, respectively to drive a corresponding word line into a selected state in response to a row select signal from row decode circuit RD.
Row related circuit RRC further includes a bit line isolation control circuit BIGa0 which outputs bit line isolation control signal BLIa0 from its output driver Da in response to a memory block address signal which is not shown and a timing signal, a sense amplifier control circuit SACa which activates and applies a sense amplifier activation signal SOa from its output driver Db to each sense amplifier SAa (SAa1, . . . ) in response to a memory block address signal and the sense amplifier activation signal, an equalize control circuit EQCa which applies an equalize instruction signal .phi.EQa to equalize circuit EQa (EQa1, . . . ) included in sense amplifier band SB#i through its output driver Dc in response to a memory block address signal and a timing signal, and a bit line isolation control circuit BIGa1 which outputs bit line isolation control signal BLIa1 from its output driver Dd for application to a bit line isolation gate IGaa (IGaa1, . . . ) in response to a memory block address signal and a timing signal.
Row related circuit RRC further includes a bit line isolation control circuit BIGb which outputs bit line isolation control signal BLIb from its output driver De for application to bit line isolation gate IGab (IGab0, IGab2, . . . ) in response to a memory block address signal and a timing signal, an equalize control circuit EQCb which outputs equalize instruction signal .phi.EQb from its output driver Df for application to equalize circuit EQb (EQb0, EQb1, . . . ) in response to a memory block address signal and a timing signal, and a sense amplifier control circuit SACb which outputs sense amplifier activation signal SOb from its output driver Dg to sense amplifier SAb (SAb0, SAb2, . . . ) in response to a memory block address signal and a timing signal.
These row related circuits operate for operations of selecting a row in memory block MB#i, and their activation timings are determined in response to a row address strobe signal /RAS which will be described below.
FIG. 11 is a diagram schematically showing the configuration of a memory cell MC shown in FIG. 10. In FIG. 11, memory cell MC includes a capacitor MQ for storing information, and an access transistor MT formed of an n channel MOS transistor connecting the storage node SN of capacitor MQ to bit line BL (or /BL). The cell plate node CP of memory capacitor MQ is provided with a fixed cell plate voltage VCP.
FIG. 12 is a diagram showing the configuration of bit line equalize circuit EQ and sense amplifier SA shown in FIG. 10. In FIG. 12, equalize circuit EQ includes an n channel MOS transistor T1 which conducts in response to equalize instruction signal .phi.EQ and electrically short-circuits nodes Nx and Ny, and n channel MOS transistors T2 and T3 which transmit a prescribed precharge voltage VBL to nodes Nx and Ny. Equalize circuit EQ corresponds to equalize circuits EQa1, EQb0 and EQb1 shown in FIG. 10. Nodes Nx and Ny are electrically connected to a corresponding bit line through a bit line isolation gate.
Sense amplifier SA includes p channel MOS transistors PQ1 and PQ2 having their gates and drains cross-coupled, n channel MOS transistors NQ1 and NQ2 having their gates and drains cross-coupled, a p channel MOS transistor PQ3 which conducts in response to a sense amplifier activation signal /SOP and transmits power supply voltage VCC to the sources of p channel MOS transistors PQ1 and PQ2, and an n channel MOS transistor NQ3 which conducts in response to a sense amplifier activation signal SON and transmits ground voltage GND to the sources of n channel MOS transistors NQ1 and NQ2. The drains of MOS transistors PQ1 and NQ1 are connected to node Nx, and the drains of MOS transistors PQ2 and NQ2 are connected to node Ny.
Sense amplifier activation signals SON and /SOP correspond to sense amplifier activation signal SOa or SOb shown in FIG. 10. Now, the operation of the semiconductor memory device shown in FIGS. 9 to 12 will be described in conjunction with FIG. 13, its operation waveform chart. In FIG. 13, operation waveforms when word line WL0 in memory block MB#i is selected are shown by way of illustration.
Before time t0, when row address strobe signal /RAS is at an H level, the semiconductor memory device is in a stand-by state. In this state, equalize instruction signal .phi.EQ is at an H level, equalize circuits EQ (EQa1, EQb0, EQb1) are all in the active states, and nodes Nx and Ny are precharged to a prescribed intermediate voltage VBL level. Bit line isolation control signals BLI (BLIa0, BLIa1, and BLIb) are at an H level, bit line isolation gates IG (IGca, IGaa1, IGab0, IGab2) are in their conductive states, and each bit line pair BLP (BLP0 to BLP2) is electrically connected to node Nx and Ny shown in FIG. 12 through a corresponding bit line isolation gate and precharged to prescribed intermediate voltage VBL level by the function of equalize circuit EQ.
Sense amplifier activation signal /SOP is at an H level, sense amplifier activation signal SON is at an L level, MOS transistors PQ3 and NQ3 for activating sense amplifiers shown in FIG. 12 are in a non-conductive state, and sense amplifier SA is in an inactive state. The signal potential on column select line CSL from the column decoder is also at an L level.
At time t0, as row address strobe signal /RAS falls to an L levels a memory cycle is initiated. In response to the falling of row address strobe signal /RAS, an address signal applied at the time is incorporated as an X address signal to produce an internal address signal. The X address signal includes a memory block address signal to designate a memory block and a row address signal to designate a word line. Since memory block MB#i is designated, bit line equalize signals .phi.EQ (.phi.EQa and .phi.EQb) to sense amplifier bands SB#i and SB#i+1 provided corresponding to memory block MB#i are brought to an L level, equalize circuit EQ is inactivated, and a precharging operation to bit line pair BLP included in memory block MB#i is stopped.
At the time, bit line isolation control signal BLIa0 is also pulled to an L level, bit line isolation gate IGca is brought into a non-conduction state, and each bit line pair in memory block MB#i-1 is isolated from sense amplifier band SB#i. Similarly, memory block MB#i+1 which is not shown is isolated from sense amplifier band SB#i+1. Therefore, sense amplifier bands SB#i and SB#i+1 are connected only to memory block MB#i in this state.
Row decode circuit RD (see FIG. 10) performs a decoding operation on the received X address signal, and generates a signal to designate word line WL0 in memory block MB#i. Word line driver WD0 drives word line WL0 to an H level accordingly. The remaining word lines WL1 to WLn are in a non-selected state, and their potentials are maintained at an L level.
When word line WL0 is selected, the transistors MT of memory cells MC connected to the selected word line WL0 conduct, and data stored in the capacitor MQ of each memory cell MC is read out onto a corresponding bit line BL. In FIG. 13, the waveform of H level data read out onto bit line BL or /BL is shown by way of illustration. In bit line pair BLP, a bit line to which a selected memory cell is not connected maintains its intermediate voltage VBL level, and provides a reference potential for memory cell data.
Then, as the potential difference between the bit lines becomes large enough, sense amplifier activation signals SON and /SOP are activated and brought into an H level and an L level, respectively MOS transistors PQ3 and NQ3 shown in FIG. 12 conduct accordingly, thus activating sense amplifier SA. MOS transistors PQ1 and PQ2 differentially amplify bit line potentials transmitted onto nodes Nx and Ny and brings a node (bit line) with a higher potential to the power supply voltage Vcc level, while driving the lower potential bit line of the bit line pair connected to nodes Nx and Ny to the ground voltage GND level.
In parallel with the row selecting operation, at time t1, column address strobe signal /CAS falls to an active L level, thus initiating a column selecting operation. In response to the falling of column address strobe signal /CAS, an address signal applied concurrently is incorporated as a Y address signal, the column decoder CD decodes the received Y address signal, and drives a column select signal transmission line CSL corresponding to a column thus addressed to a selected state (H level).
Then, data is written/read out to/from a memory cell provided at a crossing of the addressed word line WL0 and column select signal transmission line CSL. Data is read out in response to a falling of column address strobe signal /CAS, and data is written when column address strobe signal /CAS and a write enable signal /WE instructing data writing both attain an active state.
At time t2, row address strobe signal /RAS and column address strobe signal /CAS both attain an H level of inactive state, thus completing the memory cycle. In response to the rising of row address strobe signal /RAS, the potential of word line WL0 falls to an L level, then sense amplifier activation signals SON and /SOP are inactivated, bit line isolation control signals BLI all attain an H level, equalize instruction signal .phi.EQ then attains an H level, and the bit lines in memory blocks MB#i, MB#i-1 and MB#i+1 are again precharged to the intermediate voltage VBL level by the function of the bit line equalize circuit.
Meanwhile, in response to the rising of column address strobe signal /CAS, the column decoder is inactivated, and the potential of column select signal transmission line CSL in a selected state falls to an L level.
In the shared sense amplifier architecture as described above, the length of a bit line to be driven by a sense amplifier is shortened, the capacitance of load of the bit line driven by the sense amplifier is reduced accordingly, so that data read out from a memory cell can be sensed and amplified accurately and at a high speed.
In addition, only a selected memory block is driven with the remaining non-selected memory blocks being maintained in a precharged state, current consumption may be greatly reduced as compared to a case of driving all the memory blocks.
FIG. 14 is a diagram schematically showing the chip layout of a semiconductor memory device. In FIG. 14, the semiconductor memory device is formed on a rectangular chip CH having a longer side LS and a shorter side SS. The chip is divided into four regions by the central region CRL with respect to the longer side LS and the central region CRS with respect to the shorter side SS, and memory mats MM#1 to MM#4 are provided in these four regions. Memory mats MM#1 to MM#4 each having the same configuration as that shown in FIG. 9 are divided into a plurality of memory blocks and have sense amplifier bands provided between adjacent memory blocks.
Row related circuits RRC1 to RRC4 performing operations associated with a row selection are provided along the longer side of chip CH, and column decoders CD1 to CD4 for performing column selection are provided along the shorter side. Row related circuits RRC1 to RRC4 having the same configuration as that shown in FIGS. 9 and 10 each include a row decode circuit, a bit line isolation control circuits word line drives circuit, and a sense amplifier control circuit. Output drivers (which may be word line drivers) OD1 to OD4, one for each of row related circuits RRC1 to RRC4, are shown in FIG. 14. Output signal lines (or word lines) from output drivers OD1 to OD4 extend along the shorter side in corresponding memory mats MM#1 to MM#4.
In the center of central regions CRL and CRS, there is provided a master control circuit MCTL which produces an internal address signal and an internal control signal based on an externally applied address signal and a control signal and transmits the produced signals to local control circuits (including a row related circuit and a column decoder) for each of memory mats MM#1 to MM#4. A signal from master control circuit MCTL is applied to row related circuits RRC1 and RRC2 through a master control signal transmission bus MSGL1, and applied to row related circuits RRC3 and RRC4 through a master control signal transmission bus MCGL2 provided in central region CRS between memory mats MM#3 and MM#4. Row related circuits RRC1 to RRC4 drive corresponding memory mats based on signals applied through master control signal transmission buses MSGL1 and MSGL2.
If the storage capacity of a semiconductor memory device is 256 M bits, for example, memory mats MM#1 to MM#4 each has a 64 M bit-storage capacity. Therefore, in the semiconductor memory device with such a large memory capacity, the size of the semiconductor chip CH is large, and the longer side LS and shorter side SS will be long as a result. The lengths of master control signal transmission buses MSGL1 and MSGL2 are great accordingly, which increases the interconnection resistance and interconnection capacitance, and it would be difficult for master control circuit MCTL to drive master control signal transmission buses MSGL1 and MSGL2 at a high speed. A driver with an extremely large driving capability could be provided in the output stage of master control circuit MCTL for the purpose of high speed driving, but the circuit size will be increased as a result, and such circuit architecture is not suitable for high density and high integration.
A shorter side of each of memory mats MM#1 to MM#4 has a length about half that of a shorter side of semiconductor chip CH. In each of memory mats MM#1 to MM#4, the shorter side becomes long, and the generally represented signal lines SG1 to SG4 will be long. Therefore, the output loads of generally represented output drivers OD1 to OD4 are large (as a large number of transistors are connected to signal lines SG1 to SG4), and it would be difficult for output drivers OD1 to OD4 to drive corresponding signal lines SG1 to SG14 at a high speed.
If, for example, one memory mat is divided into 32 memory blocks, and one memory mat has a storage capacity of 64 M bits, the memory capacity of a memory block is 2 M bits. In this case, 1 K word lines WL and 2 K pairs of bit lines are provided in a single memory block. The number of word lines crossing bit line pair BLP should be as small as possible, because the length of a bit line is shortened, and the bit line capacitance is reduced, so that voltage change is surely generated on bit lines based on data read out from a memory cell. The voltage change by read out data in the bit lines is usually called read out voltage and in proportion to Cb/Cs. Herein, Cb is bit line capacitance and Cs is memory cell capacitance. In order to obtain more sufficient read out voltage, the number of word lines crossing bit lines is set about as many as 512 at most. Therefore, in one memory block, 512 word lines and 4 K pairs of bit lines are provided. More specifically, 4 K pairs of bit lines cross one word line, and therefore the load of the word line is extremely large due to the capacitance of the gates of memory transistors and interconnection line capacitance. Therefore, it would be difficult to drive the word line at a high speed, and therefore memory cell data cannot be read out at a high speed.
For other bit line isolation control signals or the like, the number of MOS transistors to be connected thereto is increased, and the load capacitance becomes extremely large due to the gate capacitance and interconnection line length.
Signal propagation delay due to the interconnection line capacitance and interconnection line resistance in master control signal transmission buses MSGL1 and MSGL2 and signal propagation delay due to large load capacitance and interconnection line resistance in signal lines within each memory mat MM#1 to MM#4 or word lines SG1 to SG4 impede row selecting operation at a high speed, which increases time required for accessing as well.
Furthermore also in column decoders CD1 to CD4, the output signal lines therefor, column select signal transmission lines CSL are provided over all the memory blocks along the longer side in corresponding memory mats MM#1 to MM#4. Therefore also in the column select signal transmission lines, signal propagation delay is caused by the interconnection line resistance and interconnection line capacitance involved, which impedes high speed transmission of a column select signal, and column selection cannot be performed at a high speed as a result.
As described above, signal lines provided along the shorter side and longer side of a chip are increased in length as the memory capacity of the semiconductor memory device increases, which makes it difficult to propagate signals at a high speed, and high speed accessing cannot be achieved as a result.